High quality suppliers of instruments, professional equipment and testing solutions in the Chinese electronics industry—Shanghai Jianrong Industrial Co., Ltd. JETYOO Industrial, and Jianyou (Shanghai) Measuring Instrument Co., Ltd. JETYOO INSTANTS,Authorize the first level general agent for Taiwan Pregnancy Dragon ZEROPLUS，We specialize in providing users with instruments and equipment, testing solutions, technical training, and maintenance services.

The Pregnancy Dragon ZEROPLUS Bus Protocol Test Analyzer LAP-C322000 supports all 110 bus protocols for free
Automotive Electronics
CAN 2.0
DSI Bus
FlexRay 2.1A
LIN 2.1
MVB
WTB

Computer peripheral
FWH
GPIB
Low Pin Count
LPC-SERIRQ
LPT
PCI
PECI
PS/2
SVID
USB 1.1
USB 2.0

Memory module
Compact Flash 4.1
I2C(EEPROM 24L)
I2C(EEPROM 24LCS61/24LCS62)
MICROWIRE(EEPROM 93C)
SD2.0/SDIO
SAMSUNG K9(NAND Flash)
SPI Compatible(Atmel Memory)
UNI/O

Audio Video Multimedia
AC97
DSA Interface
HD Audio
HDMI CEC
I2S
MIDA
PCM
PSB Interface
S/PDIF
STBus

ic chip
1-WIRE
1-Wire(Advanced)
3-WIRE
BDM
HPI
I2C
JTAG 2.0
MCU-51 DECODE
MICROWIRE
SLE4442
SSI Interface
ST7669
SPI
SPI PLUS
Serial Wire Debug(SWD)
UART(RS-232C/422/485)

Basic Logic Application
ARITHMETICAL LOGIC
JK FLIP-FLOP
DIGITAL LOGIC
UP DOWN COUNTER

infrared
IRDA
NEC PD6122
Philips RC-5
Philips RC-6
PT2262/PT2272

photoelectricity
7-SEGMENT LED
CCIR656
CMOS IMAGE
DALI Interface
DM114/DM115
DMX512
LCD12864
LCD1602
LG4572
S2Cwire/AS2Cwire
SCCB

Power management
BMS
HDQ
PMBus 1.1
SDQ
SMBus 2.0

telecommunications
Differential Manchester
DigRF
ISO7816 UART
KEELOQ Code Hopping
MANCHESTER
MII
MILLER
MIL-STD-1553
MODIFIED MILLER
SIGNIA 6210
SWP
WIEGAND
WWV/WWVH/WWVB

Other applications
DS1302
DS18B20
HART
KNX
IO-Link
ModBus
MODIFIED SPI
OPENTHERM 2.2
PROFIBUS
SHT11
YK-5

LAP-C322000 Performance Characteristics
Equipped with external buttons to execute logic analyzer sampling function
On the hardware of the gestational dragon logic analyzer, there is a START button. When the logic analyzer software is turned on, this button can be used to make the logic analyzer perform the sampling action. This button allows you to quickly operate the logic analyzer to obtain data on the measured substance.

compression technique
Pregnant Dragon Technology has launched waveform compression technology, which can obtain longer waveform data without increasing memory. For Example： Set the memory depth to 1M and the sampling rate to 50MHz. When the compression function is not turned on, only 20.972ms can be captured. If the compression function is turned on and sampled with the same memory depth of 1M and sampling rate of 50MHz, the waveform time can be increased to 3.999s, greatly improving the amount of data captured.

Signal filtering delay
Pregnant Dragon Technology has launched signal filtering delay technology, which can conditionally extract signals. As shown in the figure below, the filtering condition of A1 channel is set to a high level. The difference between the two can be clearly seen through the comparison of the upper and lower parallel windows. The signal filtering delay can make the filtering conditions more flexible, and users can set the filtering time state by themselves.
For Example： There is a bug in a set of DUTs on the client side. The content of the bug is that there may be read errors when the program reads. In this case, signal filtering delay can be used for conditional extraction to analyze the bug (read status is 0X5A, read command cycle is 10us). Through the signal filtering delay function, the logic analyzer can only extract the command time 10us when the value of 0X5A appears, and then analyze the occurrence of the bug.

Trigger paging technology
The Pregnancy Dragon Logic Analyzer has added Trigger Page technology, which simply means paging continuous and lengthy signal data.
With the current set memory length of one page, the trigger point is located on page *. After analyzing the data on page *, as long as the data of the tested object is the same every time and the trigger state setting remains unchanged, the Trigger Page can be set to 2 and the logic analyzer can be restarted. When the logic analyzer stops capturing data and completes display, the content in the waveform display area is the data on page 2, which is the data immediately after the end of page *.

For Example： Set the memory depth to 32K and the sampling rate to 200MHz, set the trigger page to 1, and the end point of the captured signal is 147.465us. The data is the first half of 0X47, and then capture with the same memory depth and sampling rate. When the trigger page is set to 2, the start point of the captured signal is 147.465us, which is the end point of trigger page 1. At this time, the second half of the data 0X47 can be seen.

Trigger count calculation
The pregnancy dragon logic analyzer has added the technology of Trigger Counter, which calculates the number of triggers, Trigger Counter， The function is to trigger one or more tested signals that meet the trigger value, and the user can decide which trigger point to trigger at the position that meets the trigger setting,
*When the trigger state is triggered for the first time, the Trigger Counter should be set to 1 (preset). When the trigger state is triggered for the third time, the Trigger Counter should be set to 3, and so on.

memory analysis
The Pregnancy Dragon Logic Analyzer has added a Memory Analyzer function, which can record the status of Address, READ/WRITE, and DATA in the memory analysis table for categories that use Address in the bus, such as IIC, HDQ, 3-Wire, PM, SM, IIC (EEPROM 24LX), etc., allowing users to perform bus analysis by recording and analyzing Address, READ/WRITE, and DATA.

Example of Bus Protocol Analysis - IIS Bus Protocol Analysis and Decoding
The I2S bus analysis module of Pregnancy Dragon Technology can help users perform I2S bus analysis. Through the decoding module, the Data-L and Data-R values in the signal can be directly displayed on the screen. The Pregnancy Dragon Technology IIS bus analysis module can select data bit lengths of 16, 20, 24, and 32 bits according to the I2S signal format to be tested, making it convenient for users to analyze various I2S signals smoothly.

LAP-C322000 operation and usage
Step 1: Connect the test line to the signal connection socket of the logic analyzer, and connect the other end of the test line to the test object. Depending on the condition of the test object, the test hook in the accessory can also be used to connect the test object.

Step 2: Follow the instructions in Chapter 3 of the Quick Installation Manual to set up the logic analyzer. After setting up, start the logic analyzer software and send out the signal of the test object for capture. The capture is completed as shown in the figure.
Tip: The sampling rate of the logic analyzer needs to be at least four times higher than the frequency of the target being tested to ensure the signal is correct.

Step 3: Summarize the signals into buses. Hold down the CTRL key on the keyboard and select the signal channel to be summarized with the mouse on the channel list to highlight it. After selection, right-click and select the option to summarize signals as buses. At this time, a set of designated buses will be added to the channel list.
Tip: When conducting bus analysis, the number of bus channels should be set according to the number of protocol channels to be tested. For example, IIC sets two channels and UART sets one channel.

Step 4: Right click on the newly added bus, select the bus properties, and then choose the bus analysis module to be used.
Tip: Each bus analysis module has corresponding parameter settings, and users can set them according to the content of the bus to be tested in the parameter settings.

After completing step five, the software module will display the packet values in the bus on the screen.

Tip: The logic analyzer software of Pregnancy Dragon Technology also has other powerful functions to help users perform bus analysis, such as packet list display, data search, pulse width search wait.

LAP-C322000 Accessories
Host, 125mm x 92mm x 25mm test cable, 16pin * 1/8pin * 2/2pin * 1/1pin * 1 test hook 36 pieces, USB cable, installation CD, quick installation manual, carrying bag

Pregnant Dragon Logic Analyzer=Logic Analyzer+Bus Analyzer+Logic Pen+Frequency Counter
PC-BASED LOGIC ANALYZER LAP-C SERIES
Support stacking multiple oscilloscopes for mixed signal measurement
Noble and elegant snow white texture, paired with a mini body, convenient for engineers to carry when going out.
It has stacking function, allowing you to expand measurement channels and memory depth. (Only supported by 322000)
The oscilloscope stacking function synchronously outputs status signals, allowing the logic analyzer to be used with oscilloscope stacking, meeting both digital and analog signal requirements.
More than 100 bus protocol analysis modules and customized development services are provided.
Certified through various technologies such as waveform compression, filtering and filtering delay, data comparison, memory analysis, and packet display.
Enjoy PC based interface, support Windows 2000/XP/Vista/Win7 operating systems, and use USB 2.0 (1.1) interface for data transmission and power supply.
Combining window display and user-friendly interface for data integration applications.

Logic Cube Product Specification REACH

Logic Cube comes standard with a mixed signal oscilloscope module (DSO) (optional)
Real time digital&analog mixed signal
Measurement&packet decoding three in one
USB 2.0 is an essential tool for developing products
Protocol Analyzer Module
USB 2.0 Protocol Analysis Module (optional)

Add positioning bar

The software provides two sets of positioning bars, A bar and B bar, which can measure the temporal relationship between packet data. If more than two positioning points need to be marked, multiple sets of positioning bars can be added through the new positioning bar function, up to 128 sets of positioning bars.

Bus packet list

The software can parse and display the packet status in various list protocols through the bus decoding module. In order to facilitate the analysis of list protocol signals, a bus packet list can be used in conjunction with it to display large packet data in a tree like manner in the list, allowing engineers to quickly analyze the relationship between the status of each packet.

memory analysis

Simulate the packet data parsed by the bus decoding module into a common memory map in memory for display. In terms of EEPROM, it is possible to clearly understand the read and write status of each address in the memory, accelerating the understanding of memory operation behavior.

data statistics

Users can specify the number of positive cycles, negative cycles, complete cycles, or set time periods in the channel to check if there are any conditions exceeded. If the signal cycle exceeds the set conditions, the software will indicate the channel in red font.

data comparison

The data comparison function can be used to compare the waveforms of two LA save disks (environmental parameters need to be *). The software will automatically mark the waveform difference points in the two save disks with orange red quotation marks and calculate the comparison status of the two save disks in the LOG window.

image analysis
The image analysis function is mainly designed in conjunction with the display category bus module. When the user captures the digital signal of the image, the image analysis function can restore the current image signal to an image, thereby helping the user to verify.